Formal Methods in Computer-Aided Design

Volume 1166 of the series Lecture Notes in Computer Science pp 187-201


Validity checking for combinations of theories with equality

  • Clark BarrettAffiliated withComputer Systems Laboratory, Stanford University
  • , David DillAffiliated withComputer Systems Laboratory, Stanford University
  • , Jeremy LevittAffiliated withComputer Systems Laboratory, Stanford University

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An essential component in many verification methods is a fast decision procedure for validating logical expressions. This paper presents the algorithm used in the Stanford Validity Checker (SVC) which has been used to aid several realistic hardware verification efforts. The logic for this decision procedure includes Boolean and uninterpreted functions and linear arithmetic. We have also successfully incorporated other interpreted functions, such as array operations and linear inequalities. The primary techniques which allow a complete and efficient implementation are expression sharing, heuristic rewriting, and congruence closure with interpreted functions. We discuss these techniques and present the results of initial experiments in which SVC is used as a decision procedure in PVS, resulting in dramatic speed-ups.