Workshop 17: Instruction-Level Parallelism

Euro-Par'97 Parallel Processing

Volume 1300 of the series Lecture Notes in Computer Science pp 1074-1078

Date:

Treegion scheduling for highly parallel processors

  • Sanjeev BanerjiaAffiliated withDepartment of Electrical and Computer Engineering, North Carolina State University
  • , William A. HavankiAffiliated withDepartment of Electrical and Computer Engineering, North Carolina State University
  • , Thomas M. ConteAffiliated withDepartment of Electrical and Computer Engineering, North Carolina State University

Abstract

Instruction scheduling is a compile-time technique for extracting parallelism from programs for statically scheduled instruction level parallel processors. Typically, an instruction scheduler partitions a program into regions and then schedules each region. One style of region represents a program as a set of decision trees or treegions. The non-linear nature of the treegion allows scheduling across multiple paths. This paper presents such a technique, termed treegion scheduling. The results of experiments comparing treegion scheduling to scheduling for basic blocks and across “simple linear regions” show that treegion scheduling outperforms the other techniques.