Two Dimensional Dynamic Multigrained Reconfigurable Hardware

Conference paper

DOI: 10.1007/978-94-007-1488-5_18

Volume 105 of the book series Lecture Notes in Electrical Engineering (LNEE)
Cite this paper as:
Braun L., Becker J. (2011) Two Dimensional Dynamic Multigrained Reconfigurable Hardware. In: Voros N., Mukherjee A., Sklavos N., Masselos K., Huebner M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht


Partial dynamic reconfigurable (PDR) systems designed with state-of-the-art tool chains, like the Early Access Partial Reconfiguration (EAPR) Flow from Xilinx, does not exploit the full flexibility and all features which a state of the art FPGA chip offers. For example the utilized chip area and the position of a region which can be reconfigured dynamically is traditionally specified during design-time. Thereby the shape and the size of the reconfigurable area are set by the size of the largest module to be reconfigured. The consequence is that if a smaller module is placed on that region, chip area stays unused as so called black silicon. This drawback is only one example for the limitation of development tools of reconfigurable hardware architectures. In this book section, a new approach for exploiting the capability of reconfigurable hardware architectures is presented. It allows exploiting the reconfigurable architectures more efficient than other solutions introduced before. This is achieved through a novel concept of using micro blocks for the communication infrastructure as well as for the functional elements on the FPGA. The granularity and the online versus offline tradeoff for the usage of the micro blocks for building up more complex structures on the FPGA will be presented in this chapter.

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Karlsruher Institut für Technologie (KIT) Institut für Technik der Informationsverarbeitung (ITIV)KarlsruheGermany