Abstract
For the design of sequential error detection circuits very few methods adapted to specific fault models are known. In[AS 75, SS 89] it is described how all single stuck-at faults of single gates and single memory elements can be detected by a checker. The hardware costs are relatively high and this method is based on the described specific fault model. In [HO 85] a “coding” of the actual state of the monitored sequential circuit and a “coding” of the forecasted state are compared.
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© 1991 Springer-Verlag Berlin Heidelberg
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Gössel, M. (1991). Optimal Error Detection Circuits for Sequential Circuits with Observable States. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_15
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DOI: https://doi.org/10.1007/978-3-642-76930-6_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-54545-3
Online ISBN: 978-3-642-76930-6
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