Chapter

VLSI Systems and Computations

pp 337-346

MIPS: A VLSI Processor Architecture

  • John HennessyAffiliated withDepartments of Electrical Engineering and Computer Science, Stanford University
  • , Norman JouppiAffiliated withDepartments of Electrical Engineering and Computer Science, Stanford University
  • , Forest BaskettAffiliated withDepartments of Electrical Engineering and Computer Science, Stanford University
  • , John GillAffiliated withDepartments of Electrical Engineering and Computer Science, Stanford University

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Abstract

MIPS (Microprocessor without Interlocked Pipe Stages) is a general purpose processor architecture designed to be implemented on a single VLSI chip. The main goal of the design is high performance in the execution of compiled code. The architecture is experimental since it is a radical break with the trend of modern computer architectures. The basic philosophy of MIPS is to present an instruction set that is a compiler-driven encoding of the microengine. Thus, little or no decoding is needed and the instructions correspond closely to microcode instructions. The processor is pipelined but provides no pipeline interlock hardware; this function must be provided by software.