Abstract
Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system and software application. Each abstraction level greatly facilitates the design task at the cost of paying in performance and hardware resources usage. Network time synchronization is a good example of a complex system using several abstraction levels since the traditional solutions are a software application running on top of several software and hardware layers. In this contribution we study the case where a standards-compliant network time synchronization solution is fully implemented in hardware on a FPGA chip doing without any software layer. This solution makes it possible to implement very compact, inexpensive and accurate synchronization systems to be used either stand-alone or as embedded cores. Some general aspects of the design experience are commented together with some figures of merit. As a conclusion, full hardware implementations of complex digital systems should be seen as a feasible design option, from which great performance advantages can be expected, provided that we can find a suitable set of tools and control the design development costs.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
PLDA: PLDA Home Page
Mills, D.L., Martin, J., Burbank, J., Kasch, W.: Network Time Protocol Version 4: Protocol and Algorithms Specification. RFC 5905 (Standards Track) (June 2010)
IEEE: IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. PTP Version 2 (1588-2008) (2008)
Mills, D.L.: Computer Network Time Synchronization: The Network Time Protocol. CRC Press, Inc., Boca Raton (2006)
Skeie, T., Johannessen, S., Løkstad, T., Holmeide, Ø.: Same time - Different place. ABB Review (2), 9–14 (2003)
Johannessen, S.: Time Synchronization in a Local Area Network. IEEE Control Systems Magazine 24(2), 61–69 (2004)
Holmeide, Ø., Skeie, T.: Synchronised: Switching. IET Computing and Control Engineering 17(2), 42–47 (2006)
NMEA: NMEA 0183 Standard. NMEA 0183 V 4.00 (January 2002)
Croft, W.J., Gilmore, J.: Bootstrap Protocol. RFC 951 (Draft Standard) (September 1985) Updated by RFCs 1395, 1497, 1532, 1542
Plummer, D.: Ethernet Address Resolution Protocol: Or Converting Network Protocol Addresses to 48.bit Ethernet Address for Transmission on Ethernet Hardware. RFC 826 (Standard) (November 1982) Updated by RFC 5227
Viejo, J., Juan, J., Bellido, M., Millan, A., Ruiz-de Clavijo, P.: Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation. IEEE Transactions on Instrumentation and Measurement 60(12), 3961–3963 (2011)
Digilent: Digilent Home Page
Xilinx: System Generator for DSP Getting Started Guide Release 10.1. Xilinx, Inc. (March 2008)
OpenCores: OpenCores Home Page
Chapman, K.: PicoBlaze 8-Bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II and Virtex-II PRO FPGAs. Xilinx, Inc. (November 2005)
Xilinx: ISE In-Depth Tutorial. Xilinx, Inc. (March 2011)
Xilinx: ChipScope Pro 11.1 Software and Cores User Guide. Xilinx, Inc. (April 2009)
Viejo, J., Villar, J., Juan, J., Millan, A., Ostua, E., Quiros, J.: Long-term on-chip verification of systems with logical events scattered in time. Microprocessors and Microsystems 33(5), 402–408 (2012)
Meinberg: Meinberg Funkuhren GmbH & Co. KG Home Page
Symmetricom: Symmetricom Home Page
BeagleBoard.org: BeagleBoard Home Page
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Juan, J., Viejo, J., Bellido, M.J. (2013). Network Time Synchronization: A Full Hardware Approach. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_23
Download citation
DOI: https://doi.org/10.1007/978-3-642-36157-9_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36156-2
Online ISBN: 978-3-642-36157-9
eBook Packages: Computer ScienceComputer Science (R0)