Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

  • Nikita Nikitin
  • Jordi Cortadella
Conference paper

DOI: 10.1007/978-3-642-28293-5_5

Part of the Lecture Notes in Computer Science book series (LNCS, volume 7179)
Cite this paper as:
Nikitin N., Cortadella J. (2012) Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands. In: Herkersdorf A., Römer K., Brinkschulte U. (eds) Architecture of Computing Systems – ARCS 2012. ARCS 2012. Lecture Notes in Computer Science, vol 7179. Springer, Berlin, Heidelberg

Abstract

The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. A novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.

Keywords

Chip Multiprocessing Task Mapping Power Management Extremal Optimization 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Nikita Nikitin
    • 1
  • Jordi Cortadella
    • 1
  1. 1.Universitat Politècnica de CatalunyaBarcelonaSpain

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