Chapter

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

Volume 6951 of the series Lecture Notes in Computer Science pp 1-10

A Quick Method for Energy Optimized Gate Sizing of Digital Circuits

  • Mustafa AktanAffiliated withDepartment of Electrical and Computer Eng., New Mexico State University
  • , Dursun BaranAffiliated withDepartment of Electrical Eng., University of Texas at Dallas
  • , Vojin G. OklobdzijaAffiliated withDepartment of Electrical and Computer Eng., New Mexico State University

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Abstract

Exploration of energy & delay trade-offs requires a sizing solution for minimal energy under operating delay and output load constraints. In this work, a simple method called Constant Stage Effort Ratio (CSER) is proposed for minimal energy solution of digital circuits with a given target delay. The proposed method has a linear run-time dependence on the number of logic gates that is exponential for the optimal solution. As sample cases, the proposed algorithm is applied to parallel VLSI adders with varying bit-widths at 65nm CMOS technology. CSER sizing algorithm provides more than 300x run-time improvement compared to energy optimal solution with a worst case difference of 10% in energy for a 128-bits Kogge-Stone adder.

Keywords

Circuit Sizing Energy-Efficient Design Energy-Delay Estimation Switching Activity VLSI