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Cryptographic Hardware and Embedded Systems – CHES 2011

Volume 6917 of the series Lecture Notes in Computer Science pp 1-16

An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension

  • Philipp GrabherAffiliated withDepartment of Computer Science, University of Bristol
  • , Johann GroßschädlAffiliated withFSTC, CSC Research Unit, LACS, University of Luxembourg
  • , Simon HoerderAffiliated withDepartment of Computer Science, University of Bristol
  • , Kimmo JärvinenAffiliated withDepartment of Information and Computer Science, Aalto University
  • , Dan PageAffiliated withDepartment of Computer Science, University of Bristol
  • , Stefan TillichAffiliated withDepartment of Computer Science, University of Bristol
  • , Marcin WójcikAffiliated withDepartment of Computer Science, University of Bristol

Abstract

Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

Keywords

FPGA embedded processor instruction set extension