An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture

  • Simon Hoerder
  • Marcin Wójcik
  • Stefan Tillich
  • Daniel Page
Conference paper

DOI: 10.1007/978-3-642-21040-2_11

Part of the Lecture Notes in Computer Science book series (LNCS, volume 6633)
Cite this paper as:
Hoerder S., Wójcik M., Tillich S., Page D. (2011) An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture. In: Ardagna C.A., Zhou J. (eds) Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication. WISTP 2011. Lecture Notes in Computer Science, vol 6633. Springer, Berlin, Heidelberg

Abstract

Cryptographic hash functions are an omnipresent component in security-critical software and devices; they support digital signature and data authenticity schemes, mechanisms for key derivation, pseudo-random number generation and so on. A criterion for candidate hash functions in the SHA-3 contest is resistance against side-channel analysis which is a major concern especially for mobile devices. This paper explores the implementation of said candidates on a variant of the Power-Trust platform; our results highlight a flexible solution to power analysis attacks, implying only a modest performance overhead.

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Copyright information

© IFIP International Federation for Information Processing 2011

Authors and Affiliations

  • Simon Hoerder
    • 1
  • Marcin Wójcik
    • 1
  • Stefan Tillich
    • 1
  • Daniel Page
    • 1
  1. 1.Department of Computer ScienceUniversity of BristolUK

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