High Radix Montgomery Multipliers for Residue Arithmetic Channels on FPGAs

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This work targets an efficient Montgomery Modular Multiplier for use in the channels of a Residue Number System (RNS). It is implemented on FPGA and optimized by attempting and evaluating the high radix techniques of the Montgomery Algorithm. The usual correction shift step at the end is proved to be infeasible. The resulting multiplier achieves 15ns for a modular multiplication using high radix without correction shift.