Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

  • Kris Gaj
  • Ekawat Homsirikamol
  • Marcin Rogawski
Conference paper

DOI: 10.1007/978-3-642-15031-9_18

Part of the Lecture Notes in Computer Science book series (LNCS, volume 6225)
Cite this paper as:
Gaj K., Homsirikamol E., Rogawski M. (2010) Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. In: Mangard S., Standaert FX. (eds) Cryptographic Hardware and Embedded Systems, CHES 2010. CHES 2010. Lecture Notes in Computer Science, vol 6225. Springer, Berlin, Heidelberg

Abstract

Performance in hardware has been demonstrated to be an important factor in the evaluation of candidates for cryptographic standards. Up to now, no consensus exists on how such an evaluation should be performed in order to make it fair, transparent, practical, and acceptable for the majority of the cryptographic community. In this paper, we formulate a proposal for a fair and comprehensive evaluation methodology, and apply it to the comparison of hardware performance of 14 Round 2 SHA-3 candidates. The most important aspects of our methodology include the definition of clear performance metrics, the development of a uniform and practical interface, generation of multiple sets of results for several representative FPGA families from two major vendors, and the application of a simple procedure to convert multiple sets of results into a single ranking.

Keywords

benchmarking hash functions SHA-3 FPGA 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Kris Gaj
    • 1
  • Ekawat Homsirikamol
    • 1
  • Marcin Rogawski
    • 1
  1. 1.ECE DepartmentGeorge Mason UniversityFairfaxU.S.A.

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