A Novel Cache Organization for Tiled Chip Multiprocessor

  • Xi Zhang
  • Dongsheng Wang
  • Yibo Xue
  • Haixia Wang
  • Jinglei Wang
Conference paper

DOI: 10.1007/978-3-642-03644-6_4

Part of the Lecture Notes in Computer Science book series (LNCS, volume 5737)
Cite this paper as:
Zhang X., Wang D., Xue Y., Wang H., Wang J. (2009) A Novel Cache Organization for Tiled Chip Multiprocessor. In: Dou Y., Gruber R., Joller J.M. (eds) Advanced Parallel Processing Technologies. APPT 2009. Lecture Notes in Computer Science, vol 5737. Springer, Berlin, Heidelberg

Abstract

Increased device density and working set size are driving a rise in cache capacity, which comes at the cost of high access latency. Based on the characteristic of shared data, which is accessed frequently and consumes a little capacity, a novel two-level directory organization is proposed to minimize the cache access time in this paper. In this scheme, a small Fast Directory is used to offer fast hits for a great fraction of memory accesses. Detailed simulation results show that on a 16-core tiled chip multiprocessor, this approach reduces average access latency by 17.9% compared to the general cache organization, and improves the overall performance by 13.3% on average.

Keywords

Chip Multiprocessor(CMP) Tiled Architecture Multi-level Directory Cache Organization 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Xi Zhang
    • 1
  • Dongsheng Wang
    • 1
  • Yibo Xue
    • 1
  • Haixia Wang
    • 1
  • Jinglei Wang
    • 1
  1. 1.Tsinghua National Laboratory for Information Science and Technology, Department of Computer Science & TechnologyTsinghua UniversityBeijingChina

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