International Workshop on Cryptographic Hardware and Embedded Systems

CHES 2008: Cryptographic Hardware and Embedded Systems – CHES 2008 pp 396-410

Divided Backend Duplication Methodology for Balanced Dual Rail Routing

  • Karthik Baddam
  • Mark Zwolinski
Conference paper

DOI: 10.1007/978-3-540-85053-3_25

Volume 5154 of the book series Lecture Notes in Computer Science (LNCS)
Cite this paper as:
Baddam K., Zwolinski M. (2008) Divided Backend Duplication Methodology for Balanced Dual Rail Routing. In: Oswald E., Rohatgi P. (eds) Cryptographic Hardware and Embedded Systems – CHES 2008. CHES 2008. Lecture Notes in Computer Science, vol 5154. Springer, Berlin, Heidelberg

Abstract

Dual Rail Precharge circuits offer an effective way to address Differential Power Analysis Attacks, provided routing of differential signals is fully balanced. Fat Wire [1] and Backend Duplication [2] methods address this problem. However they do not consider the effect of coupling capacitance on adjacent differential signals. In this paper we propose a new method, Divided Backend Duplication, which is based on Divided Wave Dynamic Differential Logic [3] and Backend Duplication [2], that effectively addresses balanced routing problem of Dual Rail Precharge circuits. Experimental results on an AES test circuit in 130nm technology show improvements in achieving a balanced dual rail design. Further our method can also be successfully applied to FPGAs. Results from an sbox test circuit implementation on a Xilinx FPGA are presented.

Keywords

Differential Power AnalysisDual Rail RoutingDual Rail FPGA Implementation
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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Karthik Baddam
    • 1
  • Mark Zwolinski
    • 1
  1. 1.Electronics Systems and Devices Group, School of Electronics and Computer ScienceUniversity of SouthamptonUK