Designing an Efficient Hardware Implication Accelerator for SAT Solving
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- Davis J.D., Tan Z., Yu F., Zhang L. (2008) Designing an Efficient Hardware Implication Accelerator for SAT Solving. In: Kleine Büning H., Zhao X. (eds) Theory and Applications of Satisfiability Testing – SAT 2008. SAT 2008. Lecture Notes in Computer Science, vol 4996. Springer, Berlin, Heidelberg
This paper discusses the design of a hardware accelerator for Boolean Constraint Propagation (BCP) using Field Programmable Gate Arrays (FPGA). In particular, we describe the detailed implementation of the inference engine, a key component of the accelerator that performs implications. Unlike previous efforts in FPGA assisted SAT solving, our design uses Block RAM (BRAM) to store instance information. This novel design not only facilitates fast lookup and update, but also avoids synthesizing overhead for each SAT instance. We demonstrate that SAT instances can be easily partitioned into multiple groups that can be processed by multiple inference engines in parallel. By exploiting parallelism in hardware, the BCP accelerator can infer implications in 6 to 17 clock cycles for a new variable assignment. In addition, our design supports dynamic insertion and deletion of learned clauses. Cycle accurate simulation shows that our BCP accelerator is 5~16 times faster than the conventional software based approach for BCP.
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