International Conference on Compiler Construction

CC 2008: Compiler Construction pp 178-192

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs

  • Etienne Bergeron
  • Marc Feeley
  • Jean Pierre David
Conference paper

DOI: 10.1007/978-3-540-78791-4_12

Volume 4959 of the book series Lecture Notes in Computer Science (LNCS)
Cite this paper as:
Bergeron E., Feeley M., David J.P. (2008) Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. In: Hendren L. (eds) Compiler Construction. CC 2008. Lecture Notes in Computer Science, vol 4959. Springer, Berlin, Heidelberg

Abstract

JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code from an intermediate bytecode representation. This paper considers a hardware JIT compiler targeting FPGAs, which are digital circuits configurable as needed to implement application specific circuits. Recent FPGAs in the Xilinx Virtex family are particularly attractive for hardware JIT because they are reconfigurable at run time, they contain both CPUs and reconfigurable logic, and their architecture strikes a balance of features.

In this paper we discuss the design of a hardware architecture and compiler able to dynamically enhance the instruction set with hardware specialized instructions. A prototype system based on the Xilinx Virtex family supporting hardware JIT compilation is described and evaluated.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Etienne Bergeron
    • 1
  • Marc Feeley
    • 1
  • Jean Pierre David
    • 1
  1. 1.DIROUniversité de Montréal, GRM, École Polytechnique de Montréal