Chapter

Compiler Construction

Volume 4959 of the series Lecture Notes in Computer Science pp 178-192

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs

  • Etienne BergeronAffiliated withDIRO, Université de Montréal, GRM, École Polytechnique de Montréal
  • , Marc FeeleyAffiliated withDIRO, Université de Montréal, GRM, École Polytechnique de Montréal
  • , Jean Pierre DavidAffiliated withDIRO, Université de Montréal, GRM, École Polytechnique de Montréal

Abstract

JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code from an intermediate bytecode representation. This paper considers a hardware JIT compiler targeting FPGAs, which are digital circuits configurable as needed to implement application specific circuits. Recent FPGAs in the Xilinx Virtex family are particularly attractive for hardware JIT because they are reconfigurable at run time, they contain both CPUs and reconfigurable logic, and their architecture strikes a balance of features.

In this paper we discuss the design of a hardware architecture and compiler able to dynamically enhance the instruction set with hardware specialized instructions. A prototype system based on the Xilinx Virtex family supporting hardware JIT compilation is described and evaluated.