International Conference on Embedded and Ubiquitous Computing

EUC 2007: Embedded and Ubiquitous Computing pp 507-516

A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs

  • Shih-Hsu Huang
  • Chu-Liao Wang
  • Man-Lin Huang
Conference paper

DOI: 10.1007/978-3-540-77092-3_44

Volume 4808 of the book series Lecture Notes in Computer Science (LNCS)
Cite this paper as:
Huang SH., Wang CL., Huang ML. (2007) A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. In: Kuo TW., Sha E., Guo M., Yang L.T., Shao Z. (eds) Embedded and Ubiquitous Computing. EUC 2007. Lecture Notes in Computer Science, vol 4808. Springer, Berlin, Heidelberg

Abstract

In order to enable the single-pass design methodology, the planning of power distribution should be performed as early as possible. In this paper, we will tackle this problem at the floorplan stage. First, at the block level, we will present an effective method to model the behavior of local power network structure of a reused block. Next, at the full-chip level, we will present a floorplan-based power network analysis methodology for system-on-chip (SOC) designs. The proposed methodology works well because it uses suitable models to represent the local power networks of blocks according to the properties of blocks. Experimental data shows that the new modeling technique can identify the most critical drop voltage of a reused block and the floorplan-based analysis methodology is useful for the planning of power distribution network of a SOC design.

Keywords

ModelingVoltage DropPower ConsumptionReused Block
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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Shih-Hsu Huang
    • 1
  • Chu-Liao Wang
    • 1
  • Man-Lin Huang
    • 2
  1. 1.Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, TaiwanR.O.C.
  2. 2.Office of Information Technology, Feng-Chia University, Tai Chung, TaiwanR.O.C.