Chapter

Embedded and Ubiquitous Computing

Volume 4808 of the series Lecture Notes in Computer Science pp 507-516

A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs

  • Shih-Hsu HuangAffiliated withDepartment of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan
  • , Chu-Liao WangAffiliated withDepartment of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan
  • , Man-Lin HuangAffiliated withOffice of Information Technology, Feng-Chia University, Tai Chung, Taiwan

Abstract

In order to enable the single-pass design methodology, the planning of power distribution should be performed as early as possible. In this paper, we will tackle this problem at the floorplan stage. First, at the block level, we will present an effective method to model the behavior of local power network structure of a reused block. Next, at the full-chip level, we will present a floorplan-based power network analysis methodology for system-on-chip (SOC) designs. The proposed methodology works well because it uses suitable models to represent the local power networks of blocks according to the properties of blocks. Experimental data shows that the new modeling technique can identify the most critical drop voltage of a reused block and the floorplan-based analysis methodology is useful for the planning of power distribution network of a SOC design.

Keywords

Modeling Voltage Drop Power Consumption Reused Block