A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs
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In order to enable the single-pass design methodology, the planning of power distribution should be performed as early as possible. In this paper, we will tackle this problem at the floorplan stage. First, at the block level, we will present an effective method to model the behavior of local power network structure of a reused block. Next, at the full-chip level, we will present a floorplan-based power network analysis methodology for system-on-chip (SOC) designs. The proposed methodology works well because it uses suitable models to represent the local power networks of blocks according to the properties of blocks. Experimental data shows that the new modeling technique can identify the most critical drop voltage of a reused block and the floorplan-based analysis methodology is useful for the planning of power distribution network of a SOC design.
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- A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs
- Book Title
- Embedded and Ubiquitous Computing
- Book Subtitle
- International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007. Proceedings
- pp 507-516
- Print ISBN
- Online ISBN
- Series Title
- Lecture Notes in Computer Science
- Series Volume
- Series ISSN
- Springer Berlin Heidelberg
- Copyright Holder
- Springer-Verlag Berlin Heidelberg
- Additional Links
- Voltage Drop
- Power Consumption
- Reused Block
- Industry Sectors
- eBook Packages
- Author Affiliations
- 1. Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C.
- 2. Office of Information Technology, Feng-Chia University, Tai Chung, Taiwan, R.O.C.
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