Low-Power Twiddle Factor Unit for FFT Computation

  • Teemu Pitkänen
  • Tero Partanen
  • Jarmo Takala
Conference paper

DOI: 10.1007/978-3-540-73625-7_9

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4599)
Cite this paper as:
Pitkänen T., Partanen T., Takala J. (2007) Low-Power Twiddle Factor Unit for FFT Computation. In: Vassiliadis S., Bereković M., Hämäläinen T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg

Abstract

An integral part of FFT computation are the twiddle factors, which, in software implementations, are typically stored into RAM memory implying large memory footprint and power consumption. In this paper, we propose a novel twiddle factor generator based on reduced ROM tables. The unit supports both radix-4 and mixed-radix-4/2 FFT algorithms and several transform lengths. The unit operates at a rate of one factor per clock cycle.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Teemu Pitkänen
    • 1
  • Tero Partanen
    • 1
  • Jarmo Takala
    • 1
  1. 1.Tampere University of Technology, P.O. Box 553, FIN-33101 TampereFinland

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