Parallel Memory Architecture for TTA Processor

  • Jarno K. Tanskanen
  • Teemu Pitkänen
  • Risto Mäkinen
  • Jarmo Takala
Conference paper

DOI: 10.1007/978-3-540-73625-7_29

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4599)
Cite this paper as:
Tanskanen J.K., Pitkänen T., Mäkinen R., Takala J. (2007) Parallel Memory Architecture for TTA Processor. In: Vassiliadis S., Bereković M., Hämäläinen T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg

Abstract

A conflict resolving parallel data memory system for Transport Triggered Architecture (TTA) is described. The architecture is generic and reusable to support various application specific designs. With parallel memory, more area and power consuming multi-port memory can be replaced with single-port memory modules. Number of ports can be increased over what is available on a design library for multi-port memories. In an FFT TTA example, dual-port data memory was replaced by the proposed architecture. To avoid memory conflicts, the original code was rescheduled and the TTA core was regenerated for the new schedule. The original memory required an area higher by a factor of 3.38 and energy higher by a factor of 1.70. In this case, the energy consumption of the processor core increased so that system energy consumption remained about the same. However, the original system required an area higher by a factor of 1.89.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Jarno K. Tanskanen
    • 1
  • Teemu Pitkänen
    • 1
  • Risto Mäkinen
    • 2
  • Jarmo Takala
    • 1
  1. 1.Tampere University of Technology, P.O. Box 553, FIN-33101 TampereFinland
  2. 2.Plenware Oy, P.O. Box 13, FIN-33201 TampereFinland

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