Modeling of Interconnection Networks in Massively Parallel Processor Architectures

  • Alexey Kupriyanov
  • Frank Hannig
  • Dmitrij Kissler
  • Jürgen Teich
  • Julien Lallet
  • Olivier Sentieys
  • Sébastien Pillement
Conference paper

DOI: 10.1007/978-3-540-71270-1_20

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4415)
Cite this paper as:
Kupriyanov A. et al. (2007) Modeling of Interconnection Networks in Massively Parallel Processor Architectures. In: Lukowicz P., Thiele L., Tröster G. (eds) Architecture of Computing Systems - ARCS 2007. ARCS 2007. Lecture Notes in Computer Science, vol 4415. Springer, Berlin, Heidelberg

Abstract

In this paper, we present a new concept for modeling of interconnection networks in the field of massively parallel processor embedded architectures. The main focus of the paper is on two interconnection concepts, namely, interconnect-wrapper and DyRIBox definitions of reconfigurable interconnection networks. We compare both interconnection concepts against each other and formally prove their equality. Both concepts allow to model many different reconfigurable inter-processor networks efficiently. Furthermore, we point out how to define the interconnect using an architecture description language for massively parallel processor architectures called MAML. Finally, we demonstrate the pertinence of our approach by modeling and evaluation of different reconfigurable interconnect topologies.

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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Alexey Kupriyanov
    • 1
  • Frank Hannig
    • 1
  • Dmitrij Kissler
    • 1
  • Jürgen Teich
    • 1
  • Julien Lallet
    • 2
  • Olivier Sentieys
    • 2
  • Sébastien Pillement
    • 2
  1. 1.Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-NurembergGermany
  2. 2.IRISA/R2D2, University of RennesFrance

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