Chapter

Advances in Computer Systems Architecture

Volume 2823 of the series Lecture Notes in Computer Science pp 352-364

Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor

  • Adam WigginsAffiliated withUniversity of New South Wales
  • , Harvey TuchAffiliated withUniversity of New South Wales
  • , Volkmar UhligAffiliated withUniversity of Karlsruhe
  • , Gernot HeiserAffiliated withUniversity of New South WalesNational ICT Australia

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Abstract

The StrongARM processor features virtually-addressedcaches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB on each context switch, which is very costly. We present an implementation of fast context switches on the architecture in both Linux and the L4 microkernel. It is based on using domain tags as address-space identifiers and delaying cache flushes until a clash of mappings is detected. We observe a reduction of the context-switching overheads by about an order of magnitude compared to the naive scheme presently implemented in Linux.

We also implemented sharing of TLB entries for shared pages, a natural extension of the fast-context-switch approach. Even though the TLBs of the StrongARM are quite small and a potential bottleneck, we found that benefits from sharing TLB entries are generally marginal, and can only be expected to be significant under very restrictive conditions.