Chapter

Field Programmable Logic and Application

Volume 3203 of the series Lecture Notes in Computer Science pp 354-363

Evaluating Fault Emulation on FPGA

  • Peeter EllerveeAffiliated withDepartment of Computer Engineering, Tallinn University of Technology
  • , Jaan RaikAffiliated withDepartment of Computer Engineering, Tallinn University of Technology
  • , Valentin TihhomirovAffiliated withDepartment of Computer Engineering, Tallinn University of Technology
  • , Kalle TammemäeAffiliated withDepartment of Computer Engineering, Tallinn University of Technology

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Abstract

We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to evaluate possible simulation speed possibilities, we made a feasibility study of using reconfigurable hardware by emulating circuit under analysis together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.