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International Workshop on Rewriting Logic and its Applications

WRLA 2016: Rewriting Logic and Its Applications pp 47–63Cite as

A Maude Framework for Cache Coherent Multicore Architectures

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9942))

Abstract

On shared memory multicore architectures, cache memory is used to accelerate program execution by providing quick access to recently used data, but enables multiple copies of data to co-exist during execution. Although cache coherence protocols ensure that cores do not access stale data, the organisation of data in memory and the scheduling of tasks may significantly influence the performance of a parallel program in this setting. As a step towards understanding how the data organisation impacts the performance of a given parallel program using shared memory, this paper proposes a framework defined in Maude for the executable modelling of program execution on cache coherent multicore architectures, formalising the interactions between cores executing tasks, their caches, and main memory. The framework allows the specification and comparison of program execution with different design choices for the underlying hardware architecture, such as the number of cores, the data layout in main memory, and the cache associativity.

This work is partly funded by the EU research project FP7-612985 UpScale: From Inherent Concurrency to Massive Parallelism Through Type-Based Optimisations (www.upscale-project.eu).

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Notes

  1. 1.

    The complete Maude model is available from http://folk.uio.no/~shijib/wrla2016maude.zip.

  2. 2.

    Recall that the statement forces the flushing of all modified cache lines, which does not affect the number of cache misses.

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We are grateful to the anonymous reviewers for their very thorough reviews and for giving helpful and critical feedback.

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Authors and Affiliations

  1. Department of Informatics, University of Oslo, Oslo, Norway

    Shiji Bijo, Einar Broch Johnsen, Ka I Pun & Silvia Lizeth Tapia Tarifa

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  1. Shiji Bijo
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  2. Einar Broch Johnsen
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  3. Ka I Pun
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  4. Silvia Lizeth Tapia Tarifa
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Correspondence to Shiji Bijo .

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  1. Alexandru Ioan Cuza University , Iasi, Romania

    Dorel Lucanu

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Bijo, S., Johnsen, E.B., Pun, K.I., Tapia Tarifa, S.L. (2016). A Maude Framework for Cache Coherent Multicore Architectures. In: Lucanu, D. (eds) Rewriting Logic and Its Applications. WRLA 2016. Lecture Notes in Computer Science(), vol 9942. Springer, Cham. https://doi.org/10.1007/978-3-319-44802-2_3

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  • DOI: https://doi.org/10.1007/978-3-319-44802-2_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-44801-5

  • Online ISBN: 978-3-319-44802-2

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