Chapter

Reconfigurable Computing: Architectures, Tools, and Applications

Volume 8405 of the series Lecture Notes in Computer Science pp 85-96

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure

  • Karel HeyseAffiliated withELIS Department, Ghent University
  • , Dirk StroobandtAffiliated withELIS Department, Ghent University
  • , Oliver KadlcekAffiliated withMaxeler Technologies Ltd.
  • , Oliver PellAffiliated withMaxeler Technologies Ltd.

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Abstract

It is common for large hardware designs to have a number of registers or memories of which the contents have to be changed very seldom, e.g. only at startup. The conventional way of accessing these memories is using a low-speed memory bus. This bus uses valuable hardware resources, introduces long, global connections and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used.

A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.

Keywords

FPGA HPC partial reconfiguration block RAM