On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure
- Karel HeyseAffiliated withELIS Department, Ghent University
- , Dirk StroobandtAffiliated withELIS Department, Ghent University
- , Oliver KadlcekAffiliated withMaxeler Technologies Ltd.
- , Oliver PellAffiliated withMaxeler Technologies Ltd.
It is common for large hardware designs to have a number of registers or memories of which the contents have to be changed very seldom, e.g. only at startup. The conventional way of accessing these memories is using a low-speed memory bus. This bus uses valuable hardware resources, introduces long, global connections and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used.
A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.
KeywordsFPGA HPC partial reconfiguration block RAM
- On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure
- Book Title
- Reconfigurable Computing: Architectures, Tools, and Applications
- Book Subtitle
- 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings
- pp 85-96
- Print ISBN
- Online ISBN
- Series Title
- Lecture Notes in Computer Science
- Series Volume
- Series ISSN
- Springer International Publishing
- Copyright Holder
- Springer International Publishing Switzerland
- Additional Links
- partial reconfiguration
- block RAM
- Industry Sectors
- eBook Packages
- Editor Affiliations
- 15. Ruhr-Universität Bochum
- 16. DEIB, Politecnico di Milano
- 17. Faculty of Engineering (FEUP), University of Porto
- 18. Computer Engineering Laboratory, Delft University of Technology
- Author Affiliations
- 19. ELIS Department, Ghent University, Sint-Pietersnieuwstraat 41, 9000, Gent, Belgium
- 20. Maxeler Technologies Ltd., 1 Down Place, London, W6 9JH, UK
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