Chapter

Defect and Fault Tolerance in VLSI Systems

pp 319-326

A General Model for Fault Covering Problems in Reconfigurable Arrays

  • N. HasanAffiliated withDepartment of Computer Science, University of Illinois at Urbana-Champaign
  • , J. CongAffiliated withDepartment of Computer Science, University of Illinois at Urbana-Champaign
  • , C. L. LiuAffiliated withDepartment of Computer Science, University of Illinois at Urbana-Champaign

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Abstract

An increase in chip density leads to a reduction in the yield of chip production. [Schu78] showed that in most cases, only a small number of elements in defective chips are actually defective. Thus the idea of repairing a chip after fabrication becomes very appealing. Reconfigurable chips are often used for this purpose. These chips contain redundant elements that can be used to repair the defective elements. There are many different ways to reconfigure a chip using redundant elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. In this paper we introduce a general model to represent the relationships between redundant elements and defective elements in a uniform way. This model generalizes the models discussed in previous approaches. We also give a complete characterization of the complexity of the fault covering problems for all the subcases of our model, most of which have not been studied before.