Temporal partitioning for partially-reconfigurable-field-programmable gate

  • John Spillane
  • Henry Owen
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslauteren, Germany

DOI: 10.1007/3-540-64359-1_670

Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)
Cite this paper as:
Spillane J., Owen H. (1998) Temporal partitioning for partially-reconfigurable-field-programmable gate. In: Rolim J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg

Abstract

The recent introduction of partially-reconfigurable field-programmable gate arrays (PRFPGAs) has led to the need for new algorithms suited for use with these devices. Although algorithms developed for use with field-programmable gate arrays can be applied to PRFPGAs, these algorithms do not take advantage of features available in these new devices.

This paper examines the applicability of PRFPGAs in hardware emulation systems. A partitioning algorithm known as temporal partitioning is introduced for use with PRFPGA-based hardware emulation systems.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer-Verlag 1998

Authors and Affiliations

  • John Spillane
    • 1
  • Henry Owen
    • 2
  1. 1.Department of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlanta
  2. 2.Department of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlanta

Personalised recommendations