Temporal partitioning for partially-reconfigurable-field-programmable gate
The recent introduction of partially-reconfigurable field-programmable gate arrays (PRFPGAs) has led to the need for new algorithms suited for use with these devices. Although algorithms developed for use with field-programmable gate arrays can be applied to PRFPGAs, these algorithms do not take advantage of features available in these new devices.
This paper examines the applicability of PRFPGAs in hardware emulation systems. A partitioning algorithm known as temporal partitioning is introduced for use with PRFPGA-based hardware emulation systems.
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- Temporal partitioning for partially-reconfigurable-field-programmable gate
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- Parallel and Distributed Processing
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- 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing Orlando, Florida, USA, March 30 – April 3, 1998 Proceedings
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