A miss history-based architecture for cache prefetching

  • Vidyadhar Phalke
  • B. Gopinath
Conference paper

DOI: 10.1007/3-540-60368-9_35

Volume 986 of the book series Lecture Notes in Computer Science (LNCS)
Cite this paper as:
Phalke V., Gopinath B. (1995) A miss history-based architecture for cache prefetching. In: Baler H.G. (eds) Memory Management. Lecture Notes in Computer Science, vol 986. Springer, Berlin, Heidelberg

Abstract

This paper describes a hardware controlled cache prefetching technique which uses the past behavior of misses to prefetch. We present a low cost prefetch-on-miss architecture for implementing the prefetcher. Its requirements are (1) less than 6.25% increase in the main memory size, and (2) a bidirectional address bus. We evaluate the performance of our prefetcher using trace driven simulations of ATUM and SPEC benchmark suits. For a 4-way set associative 32KB cache, with at most one prefetch on a miss, we obtain miss ratio improvements over a non-prefetching scheme in the range of 23 to 37%. This improvement is obtained at the cost of increasing the bus traffic up to 39% above the non-prefetching scheme. In comparison to the sequential method, the miss ratio improves up to 14% and the bus traffic reduces up to 17%. Similar improvements over the sequential technique are obtained for larger caches and direct mapped caches.

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Copyright information

© Springer-Verlag 1995

Authors and Affiliations

  • Vidyadhar Phalke
    • 1
  • B. Gopinath
    • 2
  1. 1.Dept. of Computer ScienceRutgers UniversityPiscatawayUSA
  2. 2.Dept. of Electrical and Computer Eng.Rutgers UniversityPiscatawayUSA