Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units
- Oleg Maslennikov
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In this paper, a method for the systematic generation of executing programs for processor element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this method, each processor element of an array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows also to derive the VHDL-description of all processor element control units in the behavioral style.
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- Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units
- Book Title
- Parallel Processing and Applied Mathematics
- Book Subtitle
- 4th International Conference, PPAM 2001 Na lęczów, Poland, September 9–12, 2001 Revised Papers
- Book Part
- pp 272-279
- Print ISBN
- Online ISBN
- Series Title
- Lecture Notes in Computer Science
- Series Volume
- Series ISSN
- Springer Berlin Heidelberg
- Copyright Holder
- Springer-Verlag Berlin Heidelberg
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- Editor Affiliations
- 4. Institute of Mathematics and Computer Science, Technical University of Czestochowa
- 5. Computer Science Department, University of Tennessee
- 6. Computer Science Department, Oklahoma State University
- 7. DTU, UNI-C, Danish Computing Centre for Research and Education
- Oleg Maslennikov (8)
- Author Affiliations
- 8. Technical University of Koszalin, ul.Partyzantow 17, 75-411, Koszalin, Poland
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