«UML»’99 — The Unified Modeling Language

Volume 1723 of the series Lecture Notes in Computer Science pp 430-444


Formalising UML State Machines for Model Checking

  • Johan LiliusAffiliated withTurku Centre for Computer Science (TUCS)
  • , Iván Porres PaltorAffiliated withTurku Centre for Computer Science (TUCS)

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The paper discusses a complete formalisation of UML state machine semantics. This formalisation is given in terms of an operational semantics and it can be used as the basis for code-generation, simulation and verification tools for UML Statecharts diagrams. The formalisation is done in two steps. First, the structure of a UML state machine is translated into a term rewriting system. In the second step, the operational semantics of state machines is defined. In addition, some problematic situations that may arise are discussed. Our formalisation is able to deal with all the features of UML state machines and it has been implemented in the vUML tool, a tool for model-checking UML models.