Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions

  • G. Theodoridis
  • S. Theoharis
  • N.D. Zervas
  • C.E. Goutis
Conference paper

DOI: 10.1007/3-540-45373-3_9

Part of the Lecture Notes in Computer Science book series (LNCS, volume 1918)
Cite this paper as:
Theodoridis G., Theoharis S., Zervas N., Goutis C. (2000) Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. In: Soudris D., Pirsch P., Barke E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg

Abstract

A new probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a new probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe the temporal and spatial correlation in terms of the associated zero delay-based parameters, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. Comparative study and analysis of benchmark circuits demonstrates the accuracy of the proposed method.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • G. Theodoridis
    • 1
  • S. Theoharis
    • 1
  • N.D. Zervas
    • 1
  • C.E. Goutis
    • 1
  1. 1.VLSI Design Lab., Dept. of Elect. and Comp. Eng.University of PatrasGreece

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