Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
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- Theodoridis G., Theoharis S., Zervas N., Goutis C. (2000) Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. In: Soudris D., Pirsch P., Barke E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg
A new probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a new probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe the temporal and spatial correlation in terms of the associated zero delay-based parameters, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. Comparative study and analysis of benchmark circuits demonstrates the accuracy of the proposed method.
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