A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors
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Spill code generated during register allocation greatly influences the overall quality of compiled code, both in terms of speed as well as size. In embedded systems, where size of memory is often a major constraint, the size of compiled code is very important. In this paper we present a framework for better generation and placement of spill code for RISC-style embedded processors. Our framework attempts to achieve efficient execution and reduce spill-induced code growth. Traditional graph-coloring allocators often make spilling decisions which are not guided by program structure or path-sensitive control flow information. Quite often, allocation decisions get heavily influenced by the choice of candidates for register residency. Especially for systems with a limited number of registers, if one is not careful to contain register pressure, it could lead to generation of a lot of spill code. We propose a framework which selectively demotes variables in a contained manner and influences the formation of live ranges. The decisions for selective demotion are made through a flow-analytic approach such that fewer spill instructions are generated. Our approach tries to keep variables as candidates for register allocation only along the paths where it is profitable to do so. We attempt to identify good local candidates for demotion, however, decisions are taken only after their global demotion costs are captured. We have implemented our framework inside the SGI MIPSPRO compiler. Our results show improvement over a Briggs-style allocator in reducing code size upto 3:5% and upto 8:2% in reducing static loads in some cases for a register set of size 8. The results are very encouraging for other parameters as well for various sizes of register sets.
- Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman. Compilers Priciples, Techniques, and Tools. Addison-Wesley Publishing Company, 1986.
- P. Bergner, P. Dahl, D. Engebretsen, and M. O’Keefe. Spill Code Minimization via Interference Region Spilling. In Proceedings of the 1997 ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 287–295, June 1997.
- P. Briggs, K. Cooper, and L. Torczon. Improvements to Graph Coloring Register Allocation. ACM Transactions on Programming Languages and Systems, 16(3):428–455, May 1994. CrossRef
- D. Callahan and B. Koblenz. Register Allocation via Hierarchical Graph Coloring. In Proceedings of the 1991 ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 192–203, June 1991.
- G. Chaitin, M. Auslander, A. Chandra, J. Cocke, M. Hopkins, and P. Markstein. Register Allocation via Coloring. Computer Languages, 6:47–57, January 1981.
- F. Chow and J. Hennessy. The Priority-based Coloring Approach to Register Allocation. ACM Transactions on Programming Languages and Systems, 12(4):501–536, October 1990. CrossRef
- K. Cooper and N. McIntosh. Enhanced Code Compression for Embedded RISC Processors. In Proceedings of the 1999 ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 139–149, May 1999.
- K. Cooper, P. Schielke, and D. Subramanian. Optimizing for Reduced Code Space using Genetic Algorithms. In Proceedings of the 1999ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embdedded Systems, pages 1–9, July 1999.
- J. Ernst, W. Evans, C. Fraser, S. Lucco, and T. Proebsting. Code Compression. In Proceedings of the 1997 ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 358–365, June 1997.
- C. Fraser, E. Myers, and A. Wendt. Analyzing and Compressing Assembly Code. SIGPLAN Notices, 19(6):117–121, June 1984. CrossRef
- P. Kolte and M. J. Harrold. Load/store Range Analysis for Global Register Allocation. In Proceedings of the 1993 ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 268–277, June 1993.
- S. Liao, S. Devadas, K. Keutzer, S. Tijang, and A. Wang. Storage Assignment to Decrease Code Size. ACM Transactions on Programming Languages and Systems, 18(3):684–691, May 1996. CrossRef
- S. Mantripragada, S. Jain, and J. Dehnert. A New Framework for Integrated Global Local Scheduling. In Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, pages 167–175, October 1998.
- C. Norris and L. L. Pollock. RAP: A PDG-based Register Allocator. Software-Practice and Experience, 28(4):401–424, April 1998. CrossRef
- A. Rao and S. Pande. Storage Assignment Optimizations to Generate Compact and Efficient Code on Embedded DSPs. In Proceedings of the 1999 ACM SIGPLAN Conference on Programming Languages Design and Implementation, pages 128–138, May 1999.
- A. Wolfe and A. Chanin. Executing Compressed Programs on an Embedded RISC Architecture. In Proceedings of the 25th IEEE/ACM International Symposium on Microarchitecture, pages 81–91, December 1992.
- A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors
- Book Title
- Languages, Compilers, and Tools for Embedded Systems
- Book Subtitle
- ACM SIGPLAN Workshop LCTES 2000 Vancouver, Canada, June 18, 2000 Proceedings
- pp 81-95
- Print ISBN
- Online ISBN
- Series Title
- Lecture Notes in Computer Science
- Series Volume
- Series ISSN
- Springer Berlin Heidelberg
- Copyright Holder
- Springer-Verlag Berlin Heidelberg
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- Editor Affiliations
- 4. Department of Computer Science, University of Virginia, School of Engineering and Applied Science
- 5. Department of Computer Engineering, Seoul National University
- Author Affiliations
- 6. Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, OH 45221, Cincinnati
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