Date: 27 May 2003

Parallel Hardware Design in B

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Abstract

We present the design of a parallel synchronous hardware component from a purely functional description of its behaviour. Starting from an abstract specification of a linear time-invariant (LTI) system in Event-B a pipelined implementation is developed. The presented approach is applicable to LTI systems that can be represented as linear constant-coefficient difference equations.

We acknowledge the support of the EU (IST-2000-30103) for the PUSSEE project (project homepage: http://www.keesda.com/pusee/)