Chapter

Correct Hardware Design and Verification Methods

Volume 2144 of the series Lecture Notes in Computer Science pp 449-464

Date:

From Operational Semantics to Denotational Semantics for Verilog

  • Zhu HuibiaoAffiliated withCentre for Applied Formal Methods, South Bank University
  • , Jonathan P. BowenAffiliated withCentre for Applied Formal Methods, South Bank University
  • , He JifengAffiliated withUnited Nations University, UNU/IIST

Abstract

This paper presents the derivation of a denotational semantics from an operational semantics for a subset of the widely used hardware description language Verilog. Our aim is to build an equivalence between the operational and denotational semantics. We propose a discrete time semantic model for Verilog. Algebraic laws are also investigated in this paper, with the ultimate aim of providing a unified set of semantic views for Verilog.