Advanced Research Working Conference on Correct Hardware Design and Verification Methods

CHARME 2001: Correct Hardware Design and Verification Methods pp 449-464

From Operational Semantics to Denotational Semantics for Verilog

  • Zhu Huibiao
  • Jonathan P. Bowen
  • He Jifeng
Conference paper

DOI: 10.1007/3-540-44798-9_34

Volume 2144 of the book series Lecture Notes in Computer Science (LNCS)

Abstract

This paper presents the derivation of a denotational semantics from an operational semantics for a subset of the widely used hardware description language Verilog. Our aim is to build an equivalence between the operational and denotational semantics. We propose a discrete time semantic model for Verilog. Algebraic laws are also investigated in this paper, with the ultimate aim of providing a unified set of semantic views for Verilog.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Zhu Huibiao
    • 1
  • Jonathan P. Bowen
    • 1
  • He Jifeng
    • 2
  1. 1.Centre for Applied Formal MethodsSouth Bank UniversityLondonUK
  2. 2.United Nations University, UNU/IISTMacauChina