Abstract
This paper presents the benefits of using a generic FPGA tool set developed at the university of Brest for programming virtual FPGA. From a high level description of the FPGA architecture, the basic tools such a placer, a router or an editor are automatically generated. The description is not constrained by any model, so that abstract architectures, such as virtual FPGAs, can directly exploit the tool set as their basic programming tools.
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References
L. Lagadec, B. Pottier Object Oriented Meta tools for Reconfigurable Architecture, Conference on Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Applications, SPIE Proceedings 4212 in Photonics East 2000, Boston, 2000.
V. Betz, J. Rose, A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999.
D. Lavenier, P. Quinton, S. Rajopadhye, Advanced Systolic Design, in Digital Signal Processing for Multimedia Systems, Chapter 23, Parhi and Nishitani Eds, March 1999.
E. Fabiani, D. Lavenier, Placement of Linear Arrays, FPL 2000: 10th International Conference on Field Programmable Logic and Applications, Villach, Austria, Aug 2000
W. Fornaciari, V. Piuri, Virtual FPGAs: Some steps behind the physical barrier. In Parallel and Distributed Processing (IPPS/SPDP’98 Workshop Proceedings), LNCS 1388, 1998.
P. Guerdoux-Jamet, D. Lavenier Systolic Filter for fast DNA Similarity Search ASAP’95, Strasbourg, France, 1995.
C. Fraser, D. Hanson, A retargetable C compiler: design and implementation, The Benjamin/Cumming Publishing Company, Inc., 1995.
L. McMurchie, C. Ebeling, PathFinder: A Negotiation-Based Performances-Driven Router for FPGAs, in FPGA’95, Monterey, CA, 1995.
J. Babb, R. Tessier, A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines’93, 1993.
V. Betz, J. Rose, Using architectural famillies to increase FPGA speed and density, in FPGA’95, Monterey, CA, 1995.
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© 2001 Springer-Verlag Berlin Heidelberg
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Lagadec, L., Lavenier, D., Fabiani, E., Pottier, B. (2001). Placing, Routing, and Editing Virtual FPGAs. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_37
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DOI: https://doi.org/10.1007/3-540-44687-7_37
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