Modeling and Verification of Out-of-Order Microprocessors in UCLID
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In this paper, we describe the modeling and verification of out-of-order microprocessors with unbounded resources using an expressive, yet efficiently decidable, quantifier-free fragment of first order logic. This logic includes uninterpreted functions, equality, ordering, constrained lambda expressions, and counter arithmetic. UCLID is a tool for specifying and verifying systems expressed in this logic. The paper makes two main contributions. First, we show that the logic is expressive enough to model components found in most modern microprocessors, independent of their actual sizes. Second, we demonstrate UCLID’s verification capabilities, ranging from full automation for bounded property checking to a high degree of automation in proving restricted classes of invariants. These techniques, coupled with a counterexample generation facility, are useful in establishing correctness of processor designs. We demonstrate UCLID’s methods using a case study of a synthetic model of an out-of-order processor where all the invariants were proved automatically.
- T. Arons and A. Pnueli. Verifying Tomasulo’s algorithm by Refinement. In Proc. VLSI Design Conference (VLSI’ 99), 1999.
- T. Arons and A. Pnueli. A comparison of two verification methods for speculative instruction execution. In Proc. Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2000), March 2000.
- C. Barrett, D. Dill, and J. Levitt. Validity checking for combinations of theories with equality. In M. Srivas and A. Camilleri, editors, Formal Methods in Computer-Aided Design (FMCAD’ 96), LNCS 1166, pages 187–201. Springer-Verlag, November 1996. CrossRef
- S. Berezin, A. Biere, E. M. Clarke, and Y. Zhu. Combining symbolic model checking with uninterpreted functions for out of order microprocessor verification. In Formal Methods in Computer-Aided Design(FMCAD’ 98), LNCS 1522. Springer-Verlag, November 1998. CrossRef
- R. E. Bryant, S. German, and M. N. Velev. Exploiting positive equality in a logic of equality with uninterpreted functions. In N. Halbwachs and D. Peled, editors, Computer-Aided Verification (CAV’ 99), LNCS 1633, pages 470–482. Springer-Verlag, July 1999. CrossRef
- R. E. Bryant, S. German, and M. N. Velev. Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):1–41, January 2001.
- R. E. Bryant, S. K. Lahiri, and S. A. Seshia. Modeling and verifying systems using a logic of counter arithmetic with lambda expressions and uninterpreted functions. In Proc. Computer-Aided Verification (CAV’02) (to appear), July 2002.
- J. R. Burch and D. L. Dill. Automated verification of pipelined microprocessor control. In D. L. Dill, editor, Computer-Aided Verification (CAV’ 94), LNCS 818, pages 68–80. Springer-Verlag, June 1994.
- Y. Gurevich. The decision problem for standard classes. The Journal of Symbolic Logic, 41(2):460–464, June 1976.
- R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Proof of correctness of a processor with reorder buffer using the completion function approach. In N. Halbwachs and D. Peled, editors, Computer-Aided Verification (CAV 1999), volume 1633 of Lecture Notes in Computer Science. Springer-Verlag, July 1999. CrossRef
- R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Verifying advanced microarchitectures that support speculation and exceptions. In A. Emerson and P. Sistla, editors, Computer-Aided Verification (CAV 2000), LNCS 1855. Springer-Verlag, July 2000. CrossRef
- R. Jhala and K. McMillan. Microarchitecture verification by compositional model checking. In G. Berry, H. Comon, and A. Finkel, editors, Computer-Aided Verification, volume 2102 of Lecture Notes in Computer Science, pages 396–410. Springer-Verlag, July 2001.
- S. Lahiri, C. Pixley, and K. Albin. Experience with term level modeling and verification of the MCORE microprocessor core. In Proc. IEEE High Level Design Validation and Test (HLDVT 2001), November 2001.
- K. McMillan. Verification of an implementation of Tomasulo’s algorithm by compositional model checking. In A. J. Hu and M. Y. Vardi, editors, Computer-Aided Verification (CAV 1998), volume 1427 of Lecture Notes in Computer Science Springer-Verlag, June 1998. CrossRef
- M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In 38th Design Automation Conference (DAC’ 01), June 2001.
- S. Owre, J. M. Rushby, and N. Shankar. PVS: A prototype verification system. In Deepak Kapur, editor, 11th International Conference on Automated Deduction (CADE), volume 607 of Lecture Notes in Artificial Intelligence, pages 748–752. Springer-Verlag, June 1992.
- J. Sawada and W. Hunt. Processor verification with precise exceptions and speculative execution. In A. J. Hu and M. Y. Vardi, editors, Computer-Aided Verification (CAV’ 98), LNCS 1427. Springer-Verlag, June 1998. CrossRef
- J. P. Shen and M. Lipasti. Fundamentals of Superscalar Processor Design. In Press, 2001.
- J. U. Skakkaebaek, R. B. Jones, and D. L. Dill. Formal verification of out-of-order execution using incremental flushing. In A. J. Hu and M. Y. Vardi, editors, Computer-Aided Verification (CAV’ 98), LNCS 1427. Springer-Verlag, June 1998.
- M. N. Velev. Using rewriting rules and positive equality to formally verify wide-issue out-of-order microprocessors with a reorder buffer. In Design, Automation and Test in Europe (DATE’ 02), pages 28–35, March 2002.
- M. N. Velev and R. E. Bryant. Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions and Branch Predication. In 37th Design Automation Conference (DAC’ 00), June 2000.
- Modeling and Verification of Out-of-Order Microprocessors in UCLID
- Book Title
- Formal Methods in Computer-Aided Design
- Book Subtitle
- 4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings
- pp 142-159
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- Series Title
- Lecture Notes in Computer Science
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- Springer Berlin Heidelberg
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- Springer-Verlag Berlin Heidelberg
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- Editor Affiliations
- 4. Department of Electrical and Computer Engineering, University of Waterloo
- 5. Strategic CAD Labs, Intel Corporation
- Author Affiliations
- 7. Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA
- 6. School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
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