Test-pattern generation for VLSI circuits in a Prolog environment
- Rajiv GuptaAffiliated withDepartment of Computer Science
Prolog eminently supports hierarchical development and mixing of descriptions at various hierarchical levels. This fact can be used in test-pattern generation by mixing the functional and implementation specifications of various modules. Only the modules that are faulty need to be expanded to their implementations and a functional description of all the other modules can be used, resulting in considerable gain in efficiency.
High-level fault injection can be easily implemented in Prolog by a hierarchical naming convention described in the paper.
Concurrent fault simulation can be viewed as an optimization of the Prolog control strategy and by saving some select (non-masking) results from previous computations, the wasteful recomputations can be avoided.
Subject IndexTesting Automatic test-pattern generation Logic programming Simulation
- Test-pattern generation for VLSI circuits in a Prolog environment
- Book Title
- Third International Conference on Logic Programming
- Book Subtitle
- Imperial College of Science and Technology, London, United Kingdom, July 14–18, 1986 Proceedings
- pp 528-535
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- Series Title
- Lecture Notes in Computer Science
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- Springer Berlin Heidelberg
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- Automatic test-pattern generation
- Logic programming
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