Speeding up random access machines by few processors

Preliminary version
  • Friedhelm Meyer auf der Heide
Contributed Papers

DOI: 10.1007/3-540-16078-7_72

Part of the Lecture Notes in Computer Science book series (LNCS, volume 210)
Cite this paper as:
Meyer auf der Heide F. (1986) Speeding up random access machines by few processors. In: Monien B., Vidal-Naquet G. (eds) STACS 86. STACS 1986. Lecture Notes in Computer Science, vol 210. Springer, Berlin, Heidelberg


Sequential and parallel random access machines (RAMs, PRAMs) with arithmetic operations + and − are considered. PRAMs may also multiply with constants. These machines work on integer inputs. It is shown that, in contrast to bit orientated models as Turing machines or log-cost RAMs, one can in many cases speed up RAMs by PRAMs with few processors. More specifically, a RAM without indirect addressing can be uniformly sped up by a PRAM with q processors by a factor (loglogq)2/logq. A similar result holds for nonuniform speed ups of RAMs with indirect addressing. Furthermore, certain networks of RAMs (such as k-dimensional grids) with q processors can be sped up significantly with only q1+τ processors. Nonuniformly, the above speed up can even be achieved for arbitrary bounded degree networks (including powerful networks such as permutation networks or Cube-Connected Cycles), if only few input variables are allowed. It is previously shown by the author, that the speed ups for RAMs are almost best possible.


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Copyright information

© Springer-Verlag 1986

Authors and Affiliations

  • Friedhelm Meyer auf der Heide
    • 1
  1. 1.FB 20-Informatik, Johann Wolfgang Goethe Universität FrankfurtFrankfurt a.M.Fed. Rep. of Germany

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