International Workshop on Cryptographic Hardware and Embedded Systems

CHES 2006: Cryptographic Hardware and Embedded Systems - CHES 2006 pp 232-241

Three-Phase Dual-Rail Pre-charge Logic

  • Marco Bucci
  • Luca Giancane
  • Raimondo Luzzi
  • Alessandro Trifiletti
Conference paper

DOI: 10.1007/11894063_19

Volume 4249 of the book series Lecture Notes in Computer Science (LNCS)
Cite this paper as:
Bucci M., Giancane L., Luzzi R., Trifiletti A. (2006) Three-Phase Dual-Rail Pre-charge Logic. In: Goubin L., Matsui M. (eds) Cryptographic Hardware and Embedded Systems - CHES 2006. CHES 2006. Lecture Notes in Computer Science, vol 4249. Springer, Berlin, Heidelberg

Abstract

This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.

Keywords

DPAdual-rail logicSABLsecurity
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Marco Bucci
    • 1
  • Luca Giancane
    • 2
  • Raimondo Luzzi
    • 1
  • Alessandro Trifiletti
    • 2
  1. 1.Infineon Technologies AG 
  2. 2.University of Rome “La Sapienza”