Chapter

Cryptographic Hardware and Embedded Systems – CHES 2005

Volume 3659 of the series Lecture Notes in Computer Science pp 354-365

Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

  • Kris TiriAffiliated withElectrical Engineering Dept., UC Los Angeles
  • , David HwangAffiliated withElectrical Engineering Dept., UC Los Angeles
  • , Alireza HodjatAffiliated withElectrical Engineering Dept., UC Los Angeles
  • , Bo-Cheng LaiAffiliated withElectrical Engineering Dept., UC Los Angeles
  • , Shenglin YangAffiliated withElectrical Engineering Dept., UC Los Angeles
  • , Patrick SchaumontAffiliated withElectrical Engineering Dept., UC Los Angeles
  • , Ingrid VerbauwhedeAffiliated withElectrical Engineering Dept., UC Los AngelesDept. ESAT/SCD-COSIC, K.U.Leuven

Abstract

Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

Keywords

side-channel attack (SCA) differential power analysis (DPA) countermeasure dual rail with precharge wave dynamic differential logic (WDDL) differential routing parasitic capacitance matching