Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

  • Thomas Popp
  • Stefan Mangard
Conference paper

DOI: 10.1007/11545262_13

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3659)
Cite this paper as:
Popp T., Mangard S. (2005) Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. In: Rao J.R., Sunar B. (eds) Cryptographic Hardware and Embedded Systems – CHES 2005. CHES 2005. Lecture Notes in Computer Science, vol 3659. Springer, Berlin, Heidelberg

Abstract

During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on implementation constraints that are costly to satisfy. For example, the capacitive load of complementary wires in an integrated circuit may need to be balanced. This article describes a novel side-channel analysis resistant logic style called MDPL that completely avoids such constraints. It is a masked and dual-rail pre-charge logic style and can be implemented using common CMOS standard cell libraries. This makes MDPL perfectly suitable for semi-custom designs.

Keywords

Side-Channel Analysis DPA Hardware Countermeasures MDPL Masking Logic Dual-Rail Pre-Charge Logic 
Download to read the full conference paper text

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Thomas Popp
    • 1
  • Stefan Mangard
    • 1
  1. 1.Institute for Applied Information Processing and Communications (IAIK)TU GrazGrazAustria

Personalised recommendations