Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

Abstract

During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on implementation constraints that are costly to satisfy. For example, the capacitive load of complementary wires in an integrated circuit may need to be balanced. This article describes a novel side-channel analysis resistant logic style called MDPL that completely avoids such constraints. It is a masked and dual-rail pre-charge logic style and can be implemented using common CMOS standard cell libraries. This makes MDPL perfectly suitable for semi-custom designs.

This work has been supported by the European Commission under the Sixth Framework Programme (Project SCARD, Contract Number IST-2002-507270).