Computer Aided Verification

Volume 3576 of the series Lecture Notes in Computer Science pp 20-23

SMT-COMP: Satisfiability Modulo Theories Competition

  • Clark BarrettAffiliated withDepartment of Computer Science, New York University
  • , Leonardo de MouraAffiliated withComputer Science Laboratory, SRI International
  • , Aaron StumpAffiliated withDepartment of Computer Science and Engineering, Washington University in St. Louis

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Decision procedures for checking satisfiability of logical formulas are crucial for many verification applications (e.g., [2,6,3]). Of particular recent interest are solvers for Satisfiability Modulo Theories (SMT). SMT solvers decide logical satisfiability (or dually, validity) with respect to a background theory in classical first-order logic with equality. Background theories useful for verification are supported, like equality and uninterpreted functions (EUF), real or integer arithmetic, and theories of bitvectors and arrays. Input formulas are often syntactically restricted; for example, to be quantifier-free or to involve only difference constraints. Some solvers support a combination of theories, or quantifiers.