Totally verified systems: Linking verified software to verified hardware

  • Jeffrey J. Joyce
Conference paper

DOI: 10.1007/0-387-97226-9_29

Part of the Lecture Notes in Computer Science book series (LNCS, volume 408)
Cite this paper as:
Joyce J.J. (1990) Totally verified systems: Linking verified software to verified hardware. In: Leeser M., Brown G. (eds) Hardware Specification, Verification and Synthesis: Mathematical Aspects. Lecture Notes in Computer Science, vol 408. Springer, New York, NY

Abstract

We describe exploratory efforts to design and verify a compiler for a formally verified microprocessor as one aspect of the eventual goal of building totally verified systems. Together with a formal proof of correctness for the microprocessor, this yields a precise and rigorously established link between the semantics of the source language and the execution of compiled code by the fabricated microchip. We describe, in particular: (1) how the limitations of real hardware influenced this proof; and (2) how the general framework provided by higher-order logic was used to formalize the compiler correctness problem for a hierarchically structured language.

Keywords

compiler correctness hardware verification machine-assisted theorem proving higher-order logic safety-critical systems 

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Copyright information

© Springer-Verlag 1990

Authors and Affiliations

  • Jeffrey J. Joyce
    • 1
  1. 1.University of CambridgeUK

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