Hardware Specification, Verification and Synthesis: Mathematical Aspects
Volume 408 of the series Lecture Notes in Computer Science pp 177201
Totally verified systems: Linking verified software to verified hardware
 Jeffrey J. JoyceAffiliated withUniversity of Cambridge
Abstract
We describe exploratory efforts to design and verify a compiler for a formally verified microprocessor as one aspect of the eventual goal of building totally verified systems. Together with a formal proof of correctness for the microprocessor, this yields a precise and rigorously established link between the semantics of the source language and the execution of compiled code by the fabricated microchip. We describe, in particular: (1) how the limitations of real hardware influenced this proof; and (2) how the general framework provided by higherorder logic was used to formalize the compiler correctness problem for a hierarchically structured language.
Keywords
compiler correctness hardware verification machineassisted theorem proving higherorder logic safetycritical systems Title
 Totally verified systems: Linking verified software to verified hardware
 Book Title
 Hardware Specification, Verification and Synthesis: Mathematical Aspects
 Book Subtitle
 Mathematical Sciences Institute Workshop Cornell University, Ithaca, New York, USA July 5–7, 1989 Proceedings
 Pages
 pp 177201
 Copyright
 1990
 DOI
 10.1007/0387972269_29
 Print ISBN
 9780387972268
 Online ISBN
 9780387348018
 Series Title
 Lecture Notes in Computer Science
 Series Volume
 408
 Series ISSN
 03029743
 Publisher
 Springer New York
 Copyright Holder
 SpringerVerlag
 Additional Links
 Topics
 Keywords

 compiler correctness
 hardware verification
 machineassisted theorem proving
 higherorder logic
 safetycritical systems
 Industry Sectors
 eBook Packages
 Editors
 Authors

 Jeffrey J. Joyce ^{(1)}
 Author Affiliations

 1. University of Cambridge, UK
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