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Analog Circuit Design pp 19–38Cite as

Low-Power Pipelined A/D Conversion

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Abstract

This paper reviews recent developments and low-power design techniques for high-speed pipelined A/D converters. The discussion spans a review of the fundamental operation principles, a summary of widely used low-power techniques, and an examination of ideas that have been proposed in recent research publications. As we will show, the best research-level designs reach a power efficiency that lies within an order of magnitude of practically achievable limits in today’s architectures. This corresponds to a 2–3 order of magnitude improvement relative to the first pipelined ADCs designed in the late 1980s and early 1990s.

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Notes

  1. 1.

    The reader may notice a similarity to cascade delta-sigma converters: perfect cancellation of the first stage quantization noise requires perfect coefficient matching between the analog and digital domains; any mismatch will “leak” a portion of the coarse quantization error into the output.

  2. 2.

    This is tolerable, e.g. in imaging applications.

References

  1. S. Masuda et al., A CMOS pipeline algorithmic A/D converter, in Proceedings of the IEEE Custom Integrated Circuits Conference, Rochester, Sept 1984, pp. 559–562

    Google Scholar 

  2. S.H. Lewis, P.R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter. IEEE J. Solid-State Circuits 22(6), 954–961 (1987)

    Article  Google Scholar 

  3. S. Sutarja, P.R. Gray, A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter. IEEE J. Solid-State Circuits 23(6), 1316–1323 (1988)

    Article  Google Scholar 

  4. S.H. Lewis et al., A 10-b 20-Msample/s analog-to-digital converter. IEEE J. Solid-State Circuits 27(3), 351–358 (1992)

    Article  Google Scholar 

  5. B. Murmann, ADC performance survey 1997–2011, [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html

  6. A.M.A. Ali et al., A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration. IEEE J. Solid-State Circuits 45(12), 2602–2612 (2010)

    Article  Google Scholar 

  7. J. Arias et al., Low-power pipeline ADC for wireless LANs. IEEE J. Solid-State Circuits 39(8), 1338–1340 (2004)

    Article  MathSciNet  Google Scholar 

  8. S. Mehta et al., An 802.11 g WLAN SoC, in ISSCC Digest Technical Papers, San Francisco, Feb, 2005, pp. 94–95

    Google Scholar 

  9. C.-C. Hsu et al., An 11b 800 MS/s time-interleaved ADC with digital background calibration, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2007, pp. 464–615

    Google Scholar 

  10. Texas Instruments, AFE5805 Datasheet. [Online]. Available: http://focus.ti.com/lit/ds/symlink/afe5805.pdf

  11. B. Murmann, A/D converter trends: Power dissipation, scaling and digitally assisted architectures, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, Sept 2008, pp. 105–112

    Google Scholar 

  12. A.N. Karanicolas et al., A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. IEEE J. Solid-State Circuits 28(12), 1207–1215 (1993)

    Article  Google Scholar 

  13. I. Mehr, L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC. IEEE J. Solid-State Circuits 35(3), 318–325 (2000)

    Article  Google Scholar 

  14. I.E. Opris et al., A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter. IEEE J. Solid-State Circuits 33(12), 1898–1903 (1998)

    Article  Google Scholar 

  15. D. Schinkel et al., A double-tail latch-type voltage sense amplifier with 18 ps setup + hold time,” in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2007, pp. 314–605

    Google Scholar 

  16. T. Sundstrom, A. Alvandpour, A kick-back reduced comparator for a 4-6-Bit 3-GS/s flash ADC in a 90 nm CMOS process, in Proceedings of the MIXDES, Ciechocinek, Poland, 2007, pp. 195–198

    Google Scholar 

  17. D.W. Cline, P.R. Gray, A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS. IEEE J. Solid-State Circuits 31(3), 294–303 (1996)

    Article  Google Scholar 

  18. Y. Chiu et al., A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J. Solid-State Circuits 39(12), 2139–2151 (2004)

    Article  MathSciNet  Google Scholar 

  19. K. Bult, Embedded analog-to-digital converters, in Proceedings of the ESSCIRC, Athens, 2009, pp. 52–64

    Google Scholar 

  20. S. Kawahito, Low-power design of pipeline A/D converters, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2006, pp. 505–512

    Google Scholar 

  21. Y.-C. Huang, T,-C. Lee, A 10b 100MS/s 4.5 mW pipelined ADC with a time sharing technique, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 300–301

    Google Scholar 

  22. P. Bogner et al., A 14b 100 MS/s digitally self-calibrated pipelined ADC in 0.13um CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Dec 2006, pp. 832–841

    Google Scholar 

  23. M. Furuta et al., A 0.06 mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 382–383

    Google Scholar 

  24. C.C. Lee, M.P. Flynn, A 12b 50MS/s 3.5 mW SAR assisted 2-stage pipeline ADC, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2010, pp. 239–240

    Google Scholar 

  25. A. Verma, B. Razavi, A 10-bit 500-MS/s 55-mW CMOS ADC. IEEE J. Solid-State Circuits 44(11), 3039–3050 (2009)

    Article  Google Scholar 

  26. W. Yang et al., A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J. Solid-State Circuits 36(12), 1931–1936 (2001)

    Article  Google Scholar 

  27. E.G. Soenen, R.L. Geiger, An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs. IEEE Trans. Circuits Syst. II 42(3), 143–153 (1995)

    Article  Google Scholar 

  28. L. Singer et al., A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2000, pp. 38–39

    Google Scholar 

  29. S.-Y. Chuang, T.L. Sculley, A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE J. Solid-State Circuits 37(6), 674–683 (2002)

    Article  Google Scholar 

  30. Min Byung-Moo et al., A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J. Solid-State Circuits 38(12), 2031–2039 (2003)

    Article  Google Scholar 

  31. K. Gulati, Lee Hae-Seung, A low-power reconfigurable analog-to-digital converter. IEEE J. Solid-State Circuits 36(12), 1900–1911 (2001)

    Article  Google Scholar 

  32. P.C. Yu, Hae-Seung Lee, A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 1996, pp. 314–315

    Google Scholar 

  33. D. Kurose et al., 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid-State Circuits 41(7), 1589–1595 (2006)

    Article  Google Scholar 

  34. S. Devarajan et al., A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC. IEEE J. Solid-State Circuits 44(12), 3305–3313 (2009)

    Article  Google Scholar 

  35. J.K.-R. Kim, B. Murmann, A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration, in Proceedings of the ESSCIRC, Sevilla, Sept 2010, pp. 378–381

    Google Scholar 

  36. P. Huang et al., SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration, in Custom Integrated Circuits Conference (CICC), 2010 IEEE, San Jose, CA, USA, 2010, pp. 1–4

    Google Scholar 

  37. Byung-Geun Lee et al., A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC. IEEE J. Solid-State Circuits 43(12), 2613–2619 (2008)

    Article  Google Scholar 

  38. Bang-Sup Song et al., A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter. IEEE J. Solid-State Circuits 23(6), 1324–1333 (1988)

    Article  Google Scholar 

  39. A.M. Abo, P.R. Gray, A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, 1998, pp. 166–169

    Google Scholar 

  40. W.C. Black, D.A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits 15(6), 1022–1029 (1980)

    Article  Google Scholar 

  41. S.K. Gupta et al., A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J. Solid-State Circuits 41(12), 2650–2657 (2006)

    Article  Google Scholar 

  42. J. Ming, S.H. Lewis, An 8b 80MSample/s pipelined ADC with background calibration, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2000, pp. 42–43

    Google Scholar 

  43. X. Wang et al., A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J. Solid-State Circuits 39(11), 1799–1808 (2004)

    Article  Google Scholar 

  44. B.R. Gregoire, Moon Un-Ku, An over-60 dB true rail-to-rail performance using correlated level shifting and an Opamp with only 30 dB loop gain. IEEE J. Solid-State Circuits 43(12), 2620–2630 (2008)

    Article  Google Scholar 

  45. M. Boulemnakher et al., A 1.2 V 4.5 mW 10b 100MS/s pipeline ADC in a 65 nm CMOS, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 250–611

    Google Scholar 

  46. B. Murmann, Limits on ADC Power Dissipation, in Analog Circuit Design, ed. by M. Steyaert et al. (Springer, Dordrecht, 2006), pp. 351–368

    Chapter  Google Scholar 

  47. H.-C. Choi et al., A 12b 50MS/s 10.2 mA 0.18 μm CMOS Nyquist ADC with a fully differential class-AB switched OP-AMP, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2008, pp. 220–221

    Google Scholar 

  48. J.K. Fiorenza et al., Comparator-based switched-capacitor circuits for scaled CMOS technologies. IEEE J. Solid-State Circuits 41(12), 2658–2668 (2006)

    Article  Google Scholar 

  49. J. Chu et al., A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2010, pp. 237–238

    Google Scholar 

  50. B. Murmann, B.E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J. Solid-State Circuits 38(12), 2040–2050 (2003)

    Article  Google Scholar 

  51. Ding-Lan Shen and Tai-Cheng Lee, A 6-Bit 800-MS/s pipelined A/D converter with open-loop amplifiers, in Symposium on VLSI Circuits Digest, June 2006, pp. 134–135

    Google Scholar 

  52. A. Nazemi et al., A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS, in Symposium on VLSI Circuits Digest, 2008, pp. 18–19

    Google Scholar 

  53. K. Poulton et al., A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2003, pp. 318–496.

    Google Scholar 

  54. I. Ahmed et al., A low-power capacitive charge pump based pipelined ADC. IEEE J. Solid-State Circuits 45(5), 1016–1027 (2010)

    Article  Google Scholar 

  55. M. Anthony et al., A process-scalable low-power charge-domain 13-bit pipeline ADC, in Symposium on VLSI Circuits Dig., Honolulu, HI, USA, 2008, pp. 222–223

    Google Scholar 

  56. J. Hu et al., A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification. IEEE J. Solid-State Circuits 44(4), 1057–1066 (2009)

    Article  Google Scholar 

  57. B. Verbruggen et al., A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS. IEEE J. Solid-State Circuits 45(10), 2080–2090 (2010)

    Article  Google Scholar 

  58. T. Toifl et al., A 1.25–5 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS. IEEE J. Solid-State Circuits 44(11), 2901–2910 (2009)

    Article  Google Scholar 

  59. C.R. Grace et al., A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration. IEEE J. Solid-State Circuits 40(5), 1038–1046 (2005)

    Article  Google Scholar 

  60. A. Panigada, I. Galton, A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction. IEEE J. Solid-State Circuits 44(12), 3314–3328 (2009)

    Article  Google Scholar 

  61. B.D. Sahoo, B. Razavi, A 12-bit 200-MHz CMOS ADC. IEEE J. Solid-State Circuits 44(9), 2366–2380 (2009)

    Article  Google Scholar 

  62. M. Daito et al., A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J. Solid-State Circuits 41(11), 2417–2423 (2006)

    Article  Google Scholar 

  63. B. Murmann, B.E. Boser, Digital domain measurement and cancellation of residue amplifier nonlinearity in pipelined ADCs. IEEE Trans. Instrum. Meas. 56(6), 2504–2514 (2007)

    Article  Google Scholar 

  64. J. Li, U.-K. Moon, Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Trans. Circuits Syst. II 50(9), 531–538 (2003)

    Article  Google Scholar 

  65. J. McNeill et al., ‘Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE J. Solid-State Circuits 40(12), 2437–2445 (2005)

    Article  Google Scholar 

  66. K.-W. Hsueh et al., A 1 V 11b 200MS/s Pipelined ADC with digital background calibration in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, 2008, pp. 546–634

    Google Scholar 

  67. J.P. Keane et al., Digital background calibration for memory effects in pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I 53(3), 511–525 (2006)

    Article  Google Scholar 

  68. E. Iroaga, B. Murmann, A 12-Bit 75-MS/s pipelined ADC using incomplete settling. IEEE J. Solid-State Circuits 42(4), 748–756 (2007)

    Article  Google Scholar 

  69. S. Kawahito et al., A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2008, pp. 117–120

    Google Scholar 

  70. T. Sundstrom et al., Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans. Circuits Syst. I 56(3), 509–518 (2009)

    Article  MathSciNet  Google Scholar 

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  1. Stanford University, 420 Via Palou Mall, Stanford, CA, 94305-4070, USA

    Boris Murmann

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  1. Boris Murmann
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Correspondence to Boris Murmann .

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  1. , Dept. Elektrotechniek, K.U.Leuven, Kardinaal Mercierlaan 94, HEVERLEE, B-3001, Belgium

    Michiel Steyaert

  2. Electrical Engineering, Mixed-signal Microelectronics Group, Technical University Eindhoven, Eindhoven, 5600 MB, Netherlands

    Arthur van Roermund

  3. , Department of Physics, University of Milan-Bicocca, Milan, Italy

    Andrea Baschirotto

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Murmann, B. (2012). Low-Power Pipelined A/D Conversion. In: Steyaert, M., van Roermund, A., Baschirotto, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1926-2_2

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