Abstract
In order to ensure trusted in–field operation of integrated circuits, it is important to develop efficient low–cost techniques to detect malicious tampering (also referred to as Hardware Trojan) that causes undesired change in functional behavior. Conventional post– manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes. Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side–channel approaches that monitor the impact of a Trojan circuit on power or current signature. Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns.
The work is funded in part by a DoD seedling grant FA-8650-08-1-7859.
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References
Agrawal, D., Baktir, S., Karakoyunlu, D., Rohatgi, P., Sunar, B.: Trojan detection using IC fingerprinting. In: IEEE Symp. on Security and Privacy, pp. 296–310 (2007)
Ravi, S., Raghunathan, A., Chakradhar, S.: Tamper resistance mechanisms for secure embedded systems. In: Intl. Conf. on VLSI Design, pp. 605–611 (2006)
DARPA BAA06-40: TRUST for Integrated Circuits, http://www.darpa.mil/BAA/BAA06-40mod1/html
Kumagai, J.: Chip Detectives. IEEE Spectrum 37, 43–49 (2000)
Amyeen, M.E., Venkataraman, S., Ojha, A., Lee, S.: Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. In: Intl. Test Conf., pp. 669–678 (2004)
Pomeranz, I., Reddy, S.M.: A Measure of Quality for n-Detection Test Sets. IEEE. Trans. on Computers. 53, 1497–1503 (2004)
Mathew, B., Saab, D.G.: Combining multiple DFT schemes with test generation. IEEE Trans. on CAD. 18, 685–696 (1999)
Adee, S.: The Hunt for the Kill Switch. IEEE Spectrum 45, 34–39 (2008)
Banga, M., Hsiao, M.S.: A Region Based Approach for the Identification of Hardware Trojans. In: Intl. Workshop on Hardware-oriented Security and Trust, pp. 40–47 (2008)
Jin, Y., Makris, Y.: Hardware Trojan Detection Using Path Delay Fingerprint. In: Intl. Workshop on Hardware-oriented Security and Trust, pp. 51–57 (2008)
Rad, R.M., Wang, X., Tehranipoor, M., Plusqellic, J.: Power Supply Signal Calibration Techniques for Improving Detection Resolution to Hardware Trojans. In: Intl. Conf. on CAD, pp. 632–639 (2008)
Chakraborty, R.S., Paul, S., Bhunia, S.: On-Demand Transparency for Improving Hardware Trojan Detectability. In: Intl. Workshop on Hardware-oriented Security and Trust, pp. 48–50 (2008)
Wolff, F., Papachristou, C., Bhunia, S., Chakraborty, R.S.: Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. In: Design, Automation and Test in Europe, pp. 1362–1365 (2008)
Geuzebroek, M.J., Van der Linden, J.T., Van de Goor, A.J.: Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. In: Intl. Test Conf., pp. 138–147 (2002)
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Chakraborty, R.S., Wolff, F., Paul, S., Papachristou, C., Bhunia, S. (2009). MERO: A Statistical Approach for Hardware Trojan Detection. In: Clavier, C., Gaj, K. (eds) Cryptographic Hardware and Embedded Systems - CHES 2009. CHES 2009. Lecture Notes in Computer Science, vol 5747. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04138-9_28
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DOI: https://doi.org/10.1007/978-3-642-04138-9_28
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