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System-on-a-Chip Verification

Methodology and Techniques

  • Book
  • © 2002

Overview

Authors:
  1. Prakash Rashinkar

    1. Cadence Design Systems, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

  2. Peter Paterson

    1. Cadence Design Systems, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

  3. Leena Singh

    1. Cadence Design Systems, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-xx
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  2. Introduction

    Pages 1-43

  3. System-level Verification

    Pages 45-66

  4. Block-level Verification

    Pages 67-127

  5. Analog/Mixed Signal Simulation

    Pages 129-151

  6. Simulation

    Pages 153-234

  7. Hardware/Software Co-verification

    Pages 235-315

  8. Static Netlist Verification

    Pages 317-345

  9. Physical Verification and Design Sign-off

    Pages 347-358

  10. Back Matter

    Pages 361-372
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Keywords

About this book

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
  1. Explanation of the objective involved in performing verification after a given design step;
  2. Features of options available;
  3. When to use a particular option;
  4. How to select an option; and
  5. Limitations of the option.
This exciting new book will be of interest to all designers and test professionals.

Authors and Affiliations

  • Cadence Design Systems, Inc., USA

    Prakash Rashinkar, Peter Paterson, Leena Singh

Bibliographic Information

  • Book Title: System-on-a-Chip Verification

  • Book Subtitle: Methodology and Techniques

  • Authors: Prakash Rashinkar, Peter Paterson, Leena Singh

  • DOI: https://doi.org/10.1007/b116428

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 2002

  • Hardcover ISBN: 978-0-7923-7279-0Published: 31 December 2000

  • Softcover ISBN: 978-1-4757-7468-9Published: 23 April 2013

  • eBook ISBN: 978-0-306-46995-4Published: 08 May 2007

  • Edition Number: 1

  • Number of Pages: XX, 372

  • Number of Illustrations: 22 b/w illustrations

  • Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Artificial Intelligence, Electrical Engineering

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