Book Volume 4727 2007

Cryptographic Hardware and Embedded Systems - CHES 2007

9th International Workshop, Vienna, Austria, September 10-13, 2007. Proceedings


ISBN: 978-3-540-74734-5 (Print) 978-3-540-74735-2 (Online)

Table of contents (32 chapters)

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  1. Front Matter

    Pages -

  2. Differential and Higher Order Attacks

    1. Chapter

      Pages 1-13

      A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter

    2. Chapter

      Pages 14-27

      Gaussian Mixture Models for Higher-Order Side Channel Analysis

    3. Chapter

      Pages 28-44

      Side Channel Cryptanalysis of a Higher Order Masking Scheme

  3. Random Number Generation and Device Identification

    1. Chapter

      Pages 45-62

      High-Speed True Random Number Generation with Logic Gates Only

    2. Chapter

      Pages 63-80

      FPGA Intrinsic PUFs and Their Use for IP Protection

  4. Logic Styles: Masking and Routing

    1. Chapter

      Pages 81-94

      Evaluation of the Masked Logic Style MDPL on a Prototype Chip

    2. Chapter

      Pages 95-106

      Masking and Dual-Rail Logic Don’t Add Up

    3. Chapter

      Pages 107-120

      DPA-Resistance Without Routing Constraints?

  5. Efficient Algorithms for Embedded Processors

    1. Chapter

      Pages 121-134

      On the Power of Bitslice Implementation on Intel Core2 Processor

    2. Chapter

      Pages 135-147

      Highly Regular Right-to-Left Algorithms for Scalar Multiplication

    3. Chapter

      Pages 148-165

      MAME: A Compression Function with Reduced Hardware Requirements

  6. Collision Attacks and Fault Analysis

    1. Chapter

      Pages 166-180

      Collision Attacks on AES-Based MAC: Alpha-MAC

    2. Chapter

      Pages 181-194

      Secret External Encodings Do Not Prevent Transient Fault Analysis

    3. Chapter

      Pages 195-208

      Two New Techniques of Side-Channel Cryptanalysis

  7. High Speed AES Implementations

    1. Chapter

      Pages 209-226

      AES Encryption Implementation and Analysis on Commodity Graphics Processing Units

    2. Chapter

      Pages 227-238

      Multi-gigabit GCM-AES Architecture Optimized for FPGAs

  8. Public-Key Cryptography

    1. Chapter

      Pages 239-255

      Arithmetic Operators for Pairing-Based Cryptography

    2. Chapter

      Pages 256-271

      FPGA Design of Self-certified Signature Verification on Koblitz Curves

    3. Chapter

      Pages 272-288

      How to Maximize the Potential of FPGA Resources for Modular Exponentiation

  9. Implementation Cost of Countermeasures

    1. Chapter

      Pages 289-302

      TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks

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