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Wafer-Level Chip-Scale Packaging

Analog and Power Semiconductor Applications

  • Book
  • © 2015

Overview

Authors:
  1. Shichun Qu

    1. Fairchild Semiconductor, San Jose, USA

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    You can also search for this author in PubMed   Google Scholar

  2. Yong Liu

    1. Fairchild Semiconductor, South Portland, USA

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    You can also search for this author in PubMed   Google Scholar

  • Covers the development of wafer level power discrete packaging with regular wafer level design concept and directly bumping technology
  • Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology
  • Presents the wafer level analog IC packaging design through fan-in and fan-out with RDLs

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Table of contents (10 chapters)

  1. Front Matter

    Pages i-xvii
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  2. Demand and Challenges for Wafer-Level Chip-Scale Analog and Power Packaging

    • Shichun Qu, Yong Liu
    Pages 1-14

  3. Fan-In Wafer-Level Chip-Scale Package

    • Shichun Qu, Yong Liu
    Pages 15-38

  4. Fan-Out Wafer-Level Chip-Scale Package

    • Shichun Qu, Yong Liu
    Pages 39-62

  5. Stackable Wafer-Level Analog Chip-Scale Package

    • Shichun Qu, Yong Liu
    Pages 63-90

  6. Wafer-Level Discrete Power Mosfet Package Design

    • Shichun Qu, Yong Liu
    Pages 91-117

  7. Wafer-Level Packaging TSV/Stack Die for Integration of Analog and Power Solution

    • Shichun Qu, Yong Liu
    Pages 119-146

  8. Thermal Management, Design, and Analysis for WLCSP

    • Shichun Qu, Yong Liu
    Pages 147-172

  9. Electrical and Multiple Physics Simulation for Analog and Power WLCSP

    • Shichun Qu, Yong Liu
    Pages 173-225

  10. WLCSP Assembly

    • Shichun Qu, Yong Liu
    Pages 227-255

  11. WLCSP Typical Reliability and Test

    • Shichun Qu, Yong Liu
    Pages 257-317

  12. Back Matter

    Pages 319-322
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Keywords

About this book

Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the roleof modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.

Reviews

“Wafer Level Chip-Scale Packaging by Qu, Shichun, Liu, Yong presents good technical insights of wafer-level chip scale packaging (WLCSP) technology, suitable for both industry and academic practitioners. … It is a good reference to demonstrate the alternate wafer-level chip scale packaging, and can serve as a very informative technical reference. … The book is valuable as a learning tool for WLCSP and its clear relevance to real-world industry practices make it useful for both students and reliability practitioners.” (Chong Leong Gan and Uda Hashim, Microelectronics Reliability, August, 2015)

Authors and Affiliations

  • Fairchild Semiconductor, San Jose, USA

    Shichun Qu

  • Fairchild Semiconductor, South Portland, USA

    Yong Liu

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