Book Volume 1965 2000

Cryptographic Hardware and Embedded Systems — CHES 2000

Second International Workshop Worcester, MA, USA, August 17–18, 2000 Proceedings


ISBN: 978-3-540-41455-1 (Print) 978-3-540-44499-2 (Online)

Table of contents (27 chapters)

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  1. Front Matter

    Pages I-XI

  2. Invited Talk

    1. Chapter

      Pages 1-24

      Software Implementation of Elliptic Curve Cryptography over Binary Fields

  3. Implementation of Elliptic Curve Cryptosystems

    1. Chapter

      Pages 25-40

      Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA

    2. Chapter

      Pages 41-56

      A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m)

    3. Chapter

      Pages 57-70

      Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor

  4. Power and Timing Analysis Attacks

    1. Chapter

      Pages 71-77

      Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies

    2. Chapter

      Pages 78-92

      Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards

    3. Chapter

      Pages 93-108

      Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems

    4. Chapter

      Pages 109-124

      A Timing Attack against RSA with the Chinese Remainder Theorem

  5. Hardware Implementation of Block Ciphers

    1. Chapter

      Pages 125-140

      A Comparative Study of Performance of AES Final Candidates Using FPGAs

    2. Chapter

      Pages 141-155

      A Dynamic FPGA Implementation of the Serpent Block Cipher

    3. Chapter

      Pages 156-163

      A 12 Gbps DES Encryptor/Decryptor Core in an FPGA

    4. Chapter

      Pages 164-174

      A 155 Mbps Triple-DES Network Encryptor

  6. Hardware Architectures

    1. Chapter

      Pages 175-190

      An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture

    2. Chapter

      Pages 191-203

      High-Speed RSA Hardware Based on Barret’s Modular Reduction Method

    3. Chapter

      Pages 204-215

      Data Integrity in Hardware for Modular Arithmetic

    4. Chapter

      Pages 216-228

      A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals

  7. Invited Talk

    1. Chapter

      Pages 229-230

      How to Explain Side-Channel Leakage to Your Kids

  8. Power Analysis Attacks

    1. Chapter

      Pages 231-237

      On Boolean and Arithmetic Masking against Differential Power Analysis

    2. Chapter

      Pages 238-251

      Using Second-Order Power Analysis to Attack DPA Resistant Software

    3. Chapter

      Pages 252-263

      Differential Power Analysis in the Presence of Hardware Countermeasures

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