Field Programmable Logic and Application

14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings

Editors:

ISBN: 978-3-540-22989-6 (Print) 978-3-540-30117-2 (Online)

Table of contents (177 chapters)

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  1. Front Matter

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  2. Plenary Keynotes

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      Pages 1-1

      FPGAs and the Era of Field Programmability

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      Pages 2-11

      Reconfigurable Systems Emerge

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      Pages 12-12

      System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?

  3. Organic and Biology Computing

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      Pages 13-22

      Hardware Accelerated Novel Protein Identification

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      Pages 23-32

      Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices

  4. Security and Cryptography 1

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      Pages 33-42

      A Key Management Architecture for Securing Off-Chip Data Transfers

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      Pages 43-53

      FPGA Implementation of Biometric Authentication System Based on Hand Geometry

  5. Platform Based Design

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      Pages 54-63

      SoftSONIC: A Customisable Modular Platform for Video Applications

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      Pages 64-73

      Deploying Hardware Platforms for SoC Validation: An Industrial Case Study

  6. Algorithms and Architectures

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      Pages 74-83

      Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes

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      Pages 84-94

      Power Analysis Attacks Against FPGA Implementations of the DES

  7. Acceleration Application 1

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      Pages 95-104

      Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer

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      Pages 105-114

      Stochastic Simulation for Biochemical Reactions on FPGA

  8. Architecture 1

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      Pages 115-124

      Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures

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      Pages 125-134

      Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine

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      Pages 135-144

      Improving FPGA Performance and Area Using an Adaptive Logic Module

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      Pages 145-157

      A Dual-V DD Low Power FPGA Architecture

  9. Physical Design 1

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      Pages 158-167

      Simultaneous Timing Driven Clustering and Placement for FPGAs

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      Pages 168-178

      Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis

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      Pages 179-188

      Compact Buffered Routing Architecture

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