Field Programmable Logic and Application

13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003 Proceedings

Editors:

ISBN: 978-3-540-40822-2 (Print) 978-3-540-45234-8 (Online)

Table of contents (146 chapters)

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  1. Front Matter

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  2. Technologies and Trends

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      Pages 1-10

      Reconfigurable Circuits Using Hybrid Hall Effect Devices

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      Pages 11-20

      Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory

  3. Communications Applications

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      Pages 21-30

      Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

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      Pages 31-40

      Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S

  4. High Level Design Tools 1

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      Pages 41-50

      An Algorithm Designer’s Workbench for Platform FPGAs

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      Pages 51-60

      Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset

  5. Reconfigurable Architectures

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      Pages 61-70

      ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

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      Pages 71-80

      Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches

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      Pages 81-90

      Arbitrating Instructions in an ρμ-Coded CCM

  6. Cryptographic Applications 1

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      Pages 91-100

      How Secure Are FPGAs in Cryptographic Applications?

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      Pages 101-110

      FPGA Implementations of the RC6 Block Cipher

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      Pages 111-120

      Very High Speed 17 Gbps SHACAL Encryption Architecture

  7. Place and Route Tools

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      Pages 121-130

      Track Placement: Orchestrating Routing Structures to Maximize Routability

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      Pages 131-140

      Quark Routing

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      Pages 141-150

      Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms

  8. Multi-context FPGAs

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      Pages 151-160

      Virtualizing Hardware with Multi-context Reconfigurable Arrays

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      Pages 161-170

      A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device

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      Pages 171-180

      Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device

  9. Cryptographic Applications 2

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      Pages 181-193

      Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES

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      Pages 194-203

      Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm

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